HBM wafer tradeoffs, ASIC revenue projections, RISC-V datacenter CPUs, Chinese GPU makers, and CUDA-on-RISC-V discussions point to a more heterogeneous AI silicon landscape. The hardware conversation is expanding from GPU performance to memory, packaging, interconnects, and supply chain sustainability.
Chunghwa Precision Test expects ASIC revenue to pass GPU revenue by 2027. The projection highlights a shift toward specialized AI chips, with consequences for TCO, workload flexibility and on-premises deployment. The real issue is the trade-off betwe...
Chinese GPU vendors are reaching scale without earning profits from GPU sales. For on-prem AI buyers, that raises questions about supplier continuity, TCO, and supply chain sovereignty beyond raw benchmarks.
At Hot Chips 2026 NVIDIA discussed CUDA for RISC-V and the role of the open ISA in NVLink Fusion systems. ServeTheHome's report signals an architectural direction: the CUDA toolchain could open to RISC-V hosts, loosening the x86 constraint in acceler...
MetaX reported a first-half profit, while China's AI GPU rival landscape remains divided. The result points to a domestic market maturing unevenly: vendor sustainability and integration with self-hosted stacks become key variables for organizations e...
SiFive's move into the data center market with BigSky signals a strategic shift: bringing RISC-V processors alongside the Nvidia ecosystem, with CUDA as the interface and enterprise Linux as the operating base. For AI infrastructure operators, this o...
Three signals from the semiconductor supply chain: Washington tries to steer South Korean investments, MediaTek enters Google's TPU landscape, Apple introduces a 2nm processor. For teams evaluating self-hosted LLMs, competition among accelerators and...
Nvidia is shifting its competitive edge beyond the GPU, toward intelligent traffic control in data center systems. Adding compute cycles is no longer enough: governing flows across accelerators, memory, and network becomes the lever for efficiency. A...
Micron said at Hot Chips 2026 that HBM requires about three times the wafer area of DDR5 for the same capacity. The ratio won't improve with future generations. Each gigabyte of HBM in a datacenter GPU removes three gigabytes of conventional DRAM cap...
