Custom ASICs, advanced nodes and packaging are becoming an industrial battleground for LLM acceleration, with Samsung 4nm, TSMC CoWoS and Google TPU economics under scrutiny. Client silicon is also adding NPU capabilities, while GPU power mods expose reliability tensions.
TSMC's 3nm and 2nm nodes and CoWoS packaging remain tight as AWS, MediaTek, and TPUs shift capacity volumes. For those evaluating on-premise AI hardware, scarcity of accelerators and interposers means longer lead times and cost pressure. Demand from ...
According to DIGITIMES, Google's TPU recoups its investment in about a year. The figure opens upside for MediaTek and Broadcom ASIC revenues and signals that custom silicon for training and inference is now a concrete economic option. The fast paybac...
On Friday Intel released Linux NPU Driver 1.38, adding official support for Ubuntu 26.04 LTS. The open-source user-space components work with the IVPU kernel driver to leverage the Core Ultra NPU, a concrete step for local AI inference on long-term s...
d-Matrix presented an inference cost model at SEMICON Taiwan 2026. The point: if token prices fall while GPU depreciation, energy and memory bandwidth costs remain rigid, margins for compute capacity providers shrink. The pressure is structural and p...
Qualcomm details the next-generation Oryon CPU, Adreno GPU, and Hexagon NPU. The move confirms that local inference becomes a primary design constraint for client chips and a strategic option for organizations evaluating self-hosted deployments and d...
A modder replaced a RTX 5090's 16-pin power connector with three 8-pin connectors, pushing the card to 900 watts and 3,400 MHz. The mod highlights the tension between peak power, power delivery reliability, and cooling, with implications for anyone u...
The new Apple A20 Pro SoC doubles the Neural Engine from 16 to 32 cores and, thanks to a 96-bit LPDDR5X bus on a 2nm process, reaches about 115 GB/s of memory bandwidth. A costly investment that signals Apple's strategic priority for local model exec...
Production of HyperAccel on Samsung's 4nm node signals dedicated LLM accelerators moving from experimentation to industrial supply logic. Tight capacity adds pressure on deliveries and wafer allocation. For self-hosted deployments, ASICs promise lowe...
SEMIFIVE has started producing its HyperAccel chips on Samsung's 4-nanometer node amid tightening production capacity. The company offers custom ASICs and LLM accelerators. The news highlights growing supply-chain pressure for inference workloads and...
