SJ Semiconductor, a Chinese advanced packaging specialist, has launched a $1.5 billion project to produce 3D integrated circuits (3DICs) for AI chips. The news, reported by Sina, marks another step in China’s production capacity expansion in a critical segment of AI hardware, set against a backdrop of export restrictions and soaring demand for powerful, efficient computing.

3D packaging is an evolutionary necessity to push chip performance beyond planar miniaturization limits. Instead of laying transistors on a single plane, multiple silicon layers are stacked and connected vertically with high-density interconnects. This approach shortens signal paths, reducing latency and energy consumption, and allows components made with different manufacturing processes (logic, memory, I/O) to be combined in a single package. For chips handling inference and training of Large Language Models, the benefits are tangible: higher memory bandwidth, better thermal efficiency, and ultimately more compute per watt.

From an AI-RADAR perspective, the SJ Semiconductor news touches several core concerns for those designing on-premise AI infrastructure. More efficient chips enabled by advanced packaging aren’t just a benchmark story—they directly impact Total Cost of Ownership. An accelerator that consumes less power or integrates more memory on-package can make self-hosted deployments more sustainable, reducing operational costs for energy and cooling, and curbing architectural complexity (for instance, lowering the need to shard models across multiple GPUs to satisfy VRAM requirements). In air-gapped environments or those with strict data residency mandates where the cloud is off the table, every hardware improvement that lowers the barrier—in space, power, and expense—broadens the scope of what can be run locally.

The geopolitical context is also worth considering. China is pouring investment into its semiconductor supply chain to reduce reliance on foreign technologies, especially after U.S. restrictions on GPU exports and advanced manufacturing tools. Projects like SJ Semiconductor’s aim to fill both upstream and downstream gaps, from packaging to final assembly, and may over time influence global component pricing and availability. For European organizations procuring LLM hardware, a diversified supply chain—not solely dependent on Taiwanese foundries or U.S. fabs—introduces a resilience factor, even if the concrete effect is hard to quantify today.

The 3D packaging race is not China’s alone: companies such as TSMC, Intel, and Samsung already field mature solutions (CoWoS, Foveros, X-Cube) and are likewise expanding capacity to meet AI chip demand. SJ Semiconductor’s initiative suggests that the market is far from saturated and that advanced packaging supply will remain a bottleneck until production capacity grows significantly. For procurement planners, this means lead times and pricing will stay volatile—a factor to weigh when scaling on-premise infrastructure.

Ultimately, the $1.5 billion investment from SJ Semiconductor reads as a signal of acceleration along the entire AI hardware supply chain, with consequences reaching all the way to the architectural choices of those who run models in-house. While software and frameworks continue to evolve, the physical substrate—increasingly three-dimensional—remains the playing field for the contest of cost, sovereignty, and performance.