The news is still a rumor, but it already has the shape of a structural signal: according to reports, Google has involved AMD in the design of its next-generation TPU. At the center of the project would be a hybrid ASIC capable of integrating CPU cores directly on the package, designed for reinforcement learning workloads where coordination between tensor compute and control logic matters as much as raw accelerator performance.

The architectural point is the real heart of the matter. Today many training and inference systems separate the accelerator from the host CPU: every exchange passes through external memory and buses, with latency and complexity costs. An ASIC with on-package CPU cores brings the two worlds closer and can reduce overhead in the decision loops typical of reinforcement learning, where an agent alternates observation, action, and update. The idea is not entirely new, but the fact that a hyperscaler like Google is exploring this path with an external partner such as AMD says a lot about the direction of custom silicon.

If confirmed, the move strengthens AMD's role in data center components and adds another piece to its semicustom strategy. Google would no longer be just a customer of an internal project: it would open to a co-design that redistributes skills and value across the supply chain. For those watching the Nvidia ecosystem, the message is that competition is no longer limited to discrete GPUs, but increasingly concerns the ability to integrate heterogeneous components into a single package.

For LLM and inference workloads, the impact may be less direct in the short term, but the trend matters for those evaluating on-premise infrastructure. Reducing the separation between CPU and accelerator tends to simplify hardware management and change TCO calculations: fewer components to orchestrate, less dependence on external buses, and potentially a different balance between CapEx and OpEx. AI-RADAR has long followed these trade-offs for self-hosted deployment; the direction suggested by this rumor is that the boundary between accelerator and host system will become increasingly blurred.

It remains to be seen whether the rumor will be confirmed and what exact role AMD will play in the project. But even as a corridor voice, it signals something broader: AI chip design is entering a phase where package-level integration matters as much as raw compute, and large cloud providers are seeking custom architectures for specific workloads. This is not a technical detail: it is a shift in incentives that could redraw the supplier map in the coming years.